The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices.
Continued reduction of size in semiconductor devices causes design trade-offs for device performance, such as drive current versus junction leakage. For example, in a field-effect transistor (FET) device, a source-side characteristic is that a smaller proximity yields a higher drive current due to a higher stress. A drain-side characteristic is that a smaller proximity causes a higher junction leakage. In addition, semiconductor devices, such as FET devices, are generally constructed using a vertical implantation process of dopants in the substrate. This causes the device to have substantially symmetric source/drain (S/D) structures in the substrate. As such, it is a design challenge to optimize both drive current performance and junction leakage.
Thus, it is desirable to have a strained asymmetric source/drain semiconductor device addressing one or more of the issues discussed above.